吴晓鹏,杨银堂,朱樟明

• 1:西安电子科技大学微电子所宽禁带半导体材料与器件教育部重点实验室
• 2:西安电子科技大学微电子所宽禁带半导体材料与器件教育部重点实验室
• 3:西安电子科技大学微电子所宽禁带半导体材料与器件教育部重点实验室 陕西西安710071
• 4:陕西西安710071

摘要(Abstract)：

衬底噪声耦合是深亚微米混合信号集成电路中常见的噪声干扰效应,严重地影响了模拟电路的性能。系统地阐述混合信号SoC中的衬底噪声耦合效应及其研究现状,讨论利用基于格林方程的边界元法对衬底建模的方法,并且分别从工艺、版图、电路等不同层次衬底噪声耦合效应的抑制方法与技术,同时对将来衬底噪声研究的发展方向以及新思路进行分析与讨论。

关键词(KeyWords)： 混合信号;衬底噪声;建模方法;EEACC:2550X;2570A

Abstract:

Keywords:

基金项目(Foundation): 国家自然科学基金资助项目(6047G046);; 国防重点实验室资助项目(51433030103D20101)

作者(Author): 吴晓鹏,杨银堂,朱樟明

参考文献(References)：

• [1]Chandrakasan A P,Brodersen R W.Low Power DigitalCMOS Design[M].Kluwer Academic Publishers,1995.
• [2]Johnson T A,Knepper R W,Marcello V,et al.Chip Sub-strate Resistance Modeling Technique for Integrated CircuitDesign[J].IEEE Trans.on Computer aided Design,1984,3(2):126 134.
• [3]Stanisic B R,Verghese N K,Carley L R,et al.AddressingSubstrate Coupling in Mixed mode IC′s:Simulation andPower Distribution Synthesis[J].IEEE Journal of SolidState Circuits,1994,29(3):226 238.
• [4]Smedes T,Van Der Meijs N P,Van Genderen A J.Extrac-tion of Circuit Models for Substrate Crosstalk[J].IEEE Int.Conf.on Computer aided Design(ICCAD),1995.199 206.
• [5]Gharpurey R,Meyer R G.Modeling and Analysis of Sub-strate Coupling in Integrated Circuits[J].IEEE Journal ofSolid State Circuits,1996,31:344 352.
• [6]Verghese N K,Allstot D J,Wolfe M A.Verification Tech-niques for Substrate Coupling and Their Application toMixed signal IC Design[J].IEEE Journal of Solid StateCircuits,1996,31(3):354 365.
• [7]Verghese N K,Allstot D J,Wolfe M A.Fast Parasitic Ex-traction for Substrate Coupling in Mixed signal ICs[J].IEEE Custom Integrated Circuits Conf.,1995:121 124.
• [8]Van Heijningen M,Badaroglu M,Donnay S,et al.SubstrateNoise Generation in Complex Digital Systems:EfficientModeling and Simulation Methodology and ExperimentalVerification[J].IEEE Journal of Solid State Circuits,2002,37:1 065 1 072.
• [9]Samavedam A,Sadate A,Mayaram A,et al.A Scalable Sub-strate Noise Coupling Model for Design of Mixed signalIC′s[J].IEEE Journal of Solid State Circuits,2000,35:895 904.
• [10]Pun A L L,Yeung T,Lau J,et al.Substrate Noise Cou-pling Through Planar Spiral Inductor[J].IEEE Journal ofSolid State Circuits,1998,33:877 884.
• [11]Casalta J M,Aragones X A,Rubio A.Substrate Noise Cou-pling Evaluation in BiCMOS Technology[J].IEEE Journalof Solid State Circuits,1997,32:598 603.
• [12]Masui S.Simulation of Substrate Coupling in Mixed signalMOS Circuits[J].in Dig.of Tech.Papers IEEE Int.Symp.on VLSI Circuits,1992.42 43.
• [13]Su D K,Loinaz M J,Masui S,et al.Experimental Resultsand Modeling Techniques for Substrate Noise in Mixedsignal Integrated Circuits[J].IEEE Journal of Solid StateCircuits,1993,28(4):420 430.
• [14]Joardar K.A Simple Approach to Modeling Crosstalk in In-tegrated Circuits[J].IEEE Journal of Solid State Circuits,1994,29:1 212 1 219.
• [15]Mitra S,Rutenbar R A,Carley L R,et al.A Methodologyfor Rapid Estimation of Substrate coupled SwitchingNoise[J].in Proc.IEEE Custom Integrated Circuits Conf.,1995.129 132.
• [16]Singh R,Sali S.Efficient Real time Modeling of SubstrateCoupling in Large Mixed signal Spice Designs,Using An-alogue HDL[J].IEE Proc.of Circuits Devices Systems,1998,145:180 184.
• [17]Verghese N K,Allstot D J.Computer aided Design Con-siderations for Mixed signal Coupling in RF IntegratedCircuits[J].IEEE Journal of Solid State Circuits,1998,33:314 323.
• [18]曾余庚,刘京生,张雪阳.边界元法与有限元法[M].西安:西安电子科技大学出版社,1991.
• [19]张国艳,黄如,Mansun Chan,等.SOI数模混合集成电路的串扰特性分析[J].半导体学报,2002,23(2):203 207.
• [20]Aragones X,Jose Luis Gonzalez,Antonio Rubio.Analysisand Solution for Switching Noise Coupling in Mixed Sig-nal ICs[M].Kluwer Academic Publishers,1999.
• [21]Albuquerque E F M,Silva M M.A Comparison by Simula-tion and by the Measurement of the Substrate Noise Gener-ated by CMOS,CSL,and CBL Digital Circuits[J].Computer aided Design of Integrated Circuits and Sys-tems,IEEE Transactions on,2005,52:734 741.
• [22]Nagata M,Nagai J,Hijikata K,et al.Physical DesignGuides for Substrate Noise Reduction in CMOS DigitalCircuits[J].IEEE Journal of Solid State Circuits,2001,36:539 549.
• [23]Soens C,Van der Plas G,Wambacq P,et al.SimulationMethodology for Analysis of Substrate Noise Impact onAnalog/RF Circuits Including Interconnect Resistance.De-sign,Automation and Test in Europe,2005.Proceedings,2005.270 275.