面向PCIE 3.0总线的扰频和去扰频器FPGA设计FPGA-based designs of scrambler and descrambler for PCI Express 3.0 bus
陆启立,黄新明,孙玲,谢星,韩赛飞,唐天泽
摘要(Abstract)：
在分析PCI Express 3.0总线物理层协议的基础上,提出一种实现扰频器和去扰频器的设计方案。利用可综合Verilog HDL语言在Vivado平台下完成电路的设计综合并下载到FPGA开发板进行测试与验证。验证结果表明,设计满足PCI Express 3.0总线物理层的要求,占用逻辑资源少,可应用到总线物理层的总体设计中。
关键词(KeyWords)： PCI Express 3.0总线;扰频器;去扰频器;现场可编程门阵列;Vivado;逻辑资源
基金项目(Foundation): 国家自然科学基金项目(61571246)~~
作者(Author): 陆启立,黄新明,孙玲,谢星,韩赛飞,唐天泽
DOI: 10.16652/j.issn.1004-373x.2018.16.012
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