非线性缓冲器时延模型研究Research of Nonlinear Buffer-Delay Model
李小琳,毛军发
摘要(Abstract)：
随着VLSI集成度与工作频率的提高,时延问题已成为影响芯片性能的关键因素之一。当工艺水平发展到深亚微米级,互连线时延比重已经占据总时延的绝大部分。为了减小互连线时延,缓冲器插入是当前一种常见且有效的方法。但插入缓冲器会引入新的时延问题,因而如何建立一个精确的缓冲器时延模型,是研究的重点。
关键词(KeyWords)： 缓冲器;时延;互连线;非线性模型
基金项目(Foundation): 国家教育部博士点基金(20040248034);; 上海应用材料基金(0401)
作者(Author): 李小琳,毛军发
参考文献(References)：
- [1]Jan M Rabaey.Digital Integrated Circuits A Design Per-spective[M].Prentice Hall,1995.
- [2]John P Uyemura.Introduction to VLSI Circuits and Systems[M].Wiley,2001.
- [3]Jason Cong,Lei He,Cheng Kok Koh,et al.PerformanceOptimization of VLSI Interconnect Layout[J].Integration,the VLSI Journal,1996,21(1 2):1 94.
- [4]Florentin Dartu,Noel Menezes,Jessica Qian,et al.A Gatedelay Model for High Speed CMOS Circuits[J].31st ACM/IEEE DAC,1994.576 580.
- [5]Alexander Korshak,Jyh Chwen Lee.An Effective CurrentSource Cell Model for VDSM Delay Calculation[J].2001 In-ternational Symposium on Quality Electronic Design,2001.296 300.
- [6]Bogdan Tutuianu,Baldick R,Johnstone M S.Nonlinear Driv-er Models for Timing and Noise Analysis[J].ComputerAided Design of Integrated Circuits and Systems,2004,23(11):1 510 1 521.
- [7]Muzhou Shao,Wong D F,Huijing Cao,et al.Explicit GateDelay Model for Timing Evalution[J].International Sympo-sium on Physical Design,2003.32 38.
- [8]Avant!Corporation.Star Hspice Manual[M].Release1999.2,June 1999.