高性能多标准可配置Viterbi译码器设计与验证Design and verification of high-performance multi-standard configurable Viterbi decoder
戴澜,马东俊
摘要(Abstract)：
为了使Viterbi译码器广泛地应用于更多标准中,结合前向回溯译码和滑窗流水技术,同时ACS(Add-CompareSelect)部件通过减规约的操作减少异或延迟,提出一种高性能可配置Viterbi译码器。该译码器支持1 2,1 3,1 4码率,约束长度在5~9之间,生成多项式任意配置等参数,同时支持GPRS,Wi MAX,IS-95 CDMA,LTE,CDMA 2000等多标准。在对译码器进行设计的基础上,基于UVM验证方法学搭建一种模块级验证平台,完成Viterbi译码器模块级的功能验证,覆盖率达到99.4%。利用Synopsys Design Compiler工具进行综合,面积为0.2 mm2;在28 nm工艺,500 MHz主频下,功耗为38.3 m W,吞吐率为1.06 Gbit/s。结果表明,此译码器具有很好的灵活可配性,在移动终端有很好的应用前景。
关键词(KeyWords)： Viterbi译码器;滑窗流水技术;多项式任意配置;UVM验证方法学;异或延迟;移动终端
基金项目(Foundation): 国家自然科学基金资助项目(61674087);国家自然科学基金资助项目(61674092)~~
作者(Author): 戴澜,马东俊
DOI: 10.16652/j.issn.1004-373x.2018.10.003
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